Table 3: Diagnostic Tests
Test
|
Description
|
Number
|
Name
|
Group A: Basic Functional Tests
|
A1
|
Register
|
Verifies that registers accessible through the PCI/PCI-E interface implement the expected read-only or read/write attributes by attempting to modify those registers.
|
A2
|
PCI Configuration
|
Checks the functionality of the PCI Base Address Register (BAR) by varying the amount of memory requested by the BAR and verifying that the BAR actually requests the correct amount of memory (without actually mapping the BAR into system memory). Refer to PCI or PCI-E specifications for details on the BAR and its addressing space.
|
A3
|
Interrupt
|
Generates a PCI interrupt and verifies that the system receives the interrupt and invokes the correct ISR. A negative test is also performed to verify that a masked interrupt does not invoke the ISR.
|
A5
|
MSI
|
Verifies that a Message Signaled Interrupt (MSI) causes an MSI message to be DMA'd to host memory. A negative test is also performed to verify that when an MSI is masked, it does not write an MSI message to host memory.
|
A6
|
Memory BIST
|
Invokes the internal chip Built-In Self Test (BIST) command to test internal memory.
|
Group B: Memory Tests
|
B1
|
TXP Scratchpad
|
The Group B tests verify all memory blocks of the Broadcom NetXtreme II adapter by writing various data patterns (0x55aa55aa, 0xaa55aa55, walking zeroes, walking ones, address, etc.) to each memory location, reading back the data, and then comparing it to the value written. The fixed data patterns are used to ensure that no memory bit is stuck high or low, while the walking zeroes/ones and address tests are used to ensure that memory writes do not corrupt adjacent memory locations.
|
B2
|
TPAT Scratchpad
|
B3
|
RXP Scratchpad
|
B4
|
COM Scratchpad
|
B5
|
CP Scratchpad
|
B6
|
MCP Scratchpad
|
B7
|
TAS Header Buffer
|
B8
|
TAS Payload Buffer
|
B9
|
RBUF via GRC
|
B10
|
RBUF via Indirect Access
|
B11
|
RBUF Cluster List
|
B12
|
TSCH List
|
B13
|
CSCH List
|
B14
|
RV2P Scratchpads
|
B15
|
TBDC Memory
|
B16
|
RBDC Memory
|
B17
|
CTX Page Table
|
B18
|
CTX Memory
|
Group C: Block Tests
|
C1
|
CPU Logic and DMA Interface
|
Verifies the basic logic functionality of all the on-chip CPUs. It also exercises the DMA interface exposed to those CPUs. The internal CPU tries to initiate DMA activities (both read and write) to system memory and then compares the values to confirm that the DMA operation completed successfully.
|
C2
|
RBUF Allocation
|
Verifies the RX buffer (RBUF) allocation interface by allocating and releasing buffers and checking that the RBUF block maintains an accurate count of the allocated and free buffers.
|
C3
|
CAM Access
|
Verifies the content-addressable memory (CAM) block by performing read, write, add, modify, and cache hit tests on the CAM associative memory.
|
C4
|
TPAT Cracker
|
Verifies the packet cracking logic block (i.e., the ability to parse TCP, IP, and UDP headers within an Ethernet frame) as well as the checksum/CRC offload logic. In this test, packets are submitted to the chip as if they were received over Ethernet and the TPAT block cracks the frame (identifying the TCP, IP, and UDP header data structures) and calculates the checksum/CRC. The TPAT block results are compared with the values expected by Broadcom NetXtreme II User Diagnostics and any errors are displayed.
|
C5
|
FIO Register
|
The Fast IO (FIO) verifies the register interface that is exposed to the internal CPUs.
|
C6
|
NVM Access and Reset-Corruption
|
Verifies non-volatile memory (NVM) accesses (both read and write) initiated by one of the internal CPUs. It tests for appropriate access arbitration among multiple entities (CPUs). It also checks for possible NVM corruption by issuing a chip reset while the NVM block is servicing data.
|
C7
|
Core-Reset Integrity
|
Verifies that the chip performs its reset operation correctly by resetting the chip multiple times, checking that the bootcode and the internal uxdiag driver loads/unloads correctly.
|
C8
|
DMA Engine
|
Verifies the functionality of the DMA engine block by performing numerous DMA read and write operations to various system and internal memory locations (and byte boundaries) with varying lengths (from 1 byte to over 4 KB, crossing the physical page boundary) and different data patterns (incremental, fixed, and random). CRC checks are performed to ensure data integrity. The DMA write test also verifies that DMA writes do not corrupt the neighboring host memory.
|
C9
|
VPD
|
Exercises the Vital Product Data (VPD) interface using PCI configuration cycles and requires a proper bootcode to be programmed into the non-volatile memory. If no VPD data is present (i.e., the VPD NVM area is all 0s), the test first initializes the VPD data area with non-zero data before starting the test and restores the original data after the test completes.
|
C11
|
FIO Events
|
Verifies that the event bits in the CPU's Fast IO (FIO) interface are triggering correctly when a particular chip events occur, such as a VPD request initiated by the host, an expansion ROM request initiated by the host, a timer event generated internally, toggling any GPIO bits, or accessing NVM.
|
Group D: Ethernet Traffic Tests
|
D1
|
MAC Loopback
|
Enables MAC loopback mode in the adapter and transmits 5000 Layer 2 packets of various sizes. As the packets are received back by Broadcom NetXtreme II User Diagnostics, they are checked for errors. Packets are returned through the MAC receive path and never reach the PHY. The adapter should not be connected to a network.
|
D2
|
PHY Loopback
|
Enables PHY loopback mode in the adapter and transmits 5000 Layer 2 packets of various sizes. As the packets are received back by Broadcom NetXtreme II User Diagnostics, they are checked for errors. Packets are returned through the PHY receive path and never reach the wire. The adapter should not be connected to a network.
|
D4
|
LSO
|
Verifies the functionality of the adapter's Large Send Offload (LSO) support by enabling MAC loopback mode and transmitting large TCP packets. As the packets are received back by Broadcom NetXtreme II User Diagnostics, they are checked for proper segmentation (according to the selected MSS size) and any other errors. The adapter should not be connected to a network.
|
D5
|
EMAC Statistics
|
Verifies that the basic statistics information maintained by the chip is correct by enabling MAC loopback mode and sending Layer 2 packets of various sizes. The adapter should not be connected to a network.
|
D6
|
RPC
|
Verifies the Receive Path Catch-up (RPC) block by sending packets to different transmit chains. The packets traverse the RPC logic (though not the entire MAC block) and return to the receive buffers as received packets. This is another loopback path that is used by Layer 4 and Layer 5 traffic within the MAC block. As packets are received back by Broadcom NetXtreme II User Diagnostics, they are checked for errors. The adapter should not be connected to a network.
|